--  DesignWare DDR Explorer enables designers to optimize memory subsystems
       for power, performance and cost through a graphical simulation and
       analysis environment
   --  Explore and adjust Synopsys' DesignWare DDR Memory Controller
       configurations to achieve up to 20 percent improvement in memory
       bandwidth
   --  Optimize address mapping, clock frequency and quality of service to
       select lower cost, lower power DRAM memories
   --  Achieve 10X faster turnaround time compared to RTL analysis with
       transaction-level simulation to visualize performance and conduct
       performance sensitivity analysis
Synopsys has announced the new DesignWare DDR Explorer performance analysis tool, which enables designers to quickly optimize Synopsys' DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) for performance, power and cost. Using DDR Explorer, designers can analyze their DDR memory subsystem and optimize their architecture to increase efficiency by up to 20 percent, while achieving 10X faster turnaround time compared to RTL analysis. With the graphical simulation and analysis provided by DDR Explorer, designers can quickly select the right memory type for the lowest bill of material (BOM) cost and system power. DDR Explorer supports all of the industry standard DRAM interfaces for mobile and enterprise applications, including LPDDR2, LPDDR3, DDR2, DDR3 and DDR4.

DDR Explorer integrates a transaction-level architecture model of the DesignWare DDR Enhanced Universal Memory Controller with a graphical simulation and analysis environment that enables designers to define, run and analyze hundreds of scenarios to identify the best memory controller configuration. RTL-based performance checking, while required for final validation, typically has longer turnaround times and limits the practical number of design explorations during a project to fewer than 25. DDR Explorer enables thorough performance and power sensitivity analysis for over 250 simulations in the same amount of time. By identifying heavy traffic conditions and bottlenecks, designers can explore the DDR memory controller parameter configurations and register settings to optimize the DDR memory performance. This results in up to 20 percent greater memory efficiency, lower power consumption and lower memory cost, without sacrificing other memory performance requirements. The optimized configuration from DDR Explorer is used for DDR memory controller RTL IP configuration and performance validation, speeding the implementation and verification of the IP.

"With DDR Explorer, designers can rapidly configure, simulate and analyze the DDR memory controller and PHY subsystem," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "DDR Explorer enables designers to significantly reduce the effort of integrating DesignWare DDR Enhanced Universal Memory Controller and PHY IP into their SoCs for faster time-to-market."

Availability & Resources

DesignWare DDR Explorer is available now.

       --  Learn more about DesignWare DDR Explorer at:
           http://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr_explorer

Anyone who has ever toasted the top of their legs with their laptop or broiled their ear on a cell phone knows that microelectronic devices can give off a lot of heat. These devices contain a multitude of transistors, and although each one produces very little heat individually, their combined thermal output is significant and can damage the device.

Thermal management is an ongoing struggle for the electronics industry as there is currently no way to accurately measure temperature at the scale of individual microelectronic devices. Overheating is an even bigger problem for the roomfuls of servers needed in data storage.

Although their small size helps make transistors and other microelectronic devices useful, it foils attempts to determine which areas in the device are hottest. The mere introduction of a probe, typically larger than the microelectronic device itself, affects the device's temperature and precludes an accurate reading. As a result, microelectronic device manufacturers must rely on simulations alone to understand the temperatures inside individual devices.

"If you just simulated the temperature in a microelectronic device, the next thing you want to do is measure the temperature and see if you're right," said Matthew Mecklenburg, a senior staff scientist at the University of Southern California's Center for Electron Microscopy and Microanalysis (CEMMA). "But a persistent question has been how to make these measurements."

Associated with the USC Viterbi School of Engineering and the USC Dana and David Dornsife College of Letters, Arts and Sciences, USC CEMMA provides research tools for imaging, visualization, and analysis of nano-scale features and structures.

In a paper published in Science on February 6, a research team led by Mecklenburg and Chris Regan of University of California Los Angeles (UCLA), presented findings that are a major step forward in understanding temperatures in microelectronic devices.

To avoid altering the device's temperature they decided to forego a thermometric probe altogether. They realized that the material being imaged could act as its own thermometer.

All materials change volume depending on their temperature. Therefore, a material's temperature can be determined by carefully measuring its volume, or equivalently, its density. In this case, aluminum was used because its thermal expansion is relatively large.

To measure its density the team aimed the imaging beam from a transmission electron microscope (TEM) at the aluminum, which caused the charges within the aluminum to oscillate. These charge oscillations, or plasmons, have long been known to shift depending on a material's density, but until now they had not been analyzed carefully enough to extract a local temperature measurement. Using the TEM and electron energy loss spectroscopy (EELS), the team was able to quantify the energy of the aluminum plasmon and precisely determine its temperature with nanometer-scale resolution.

"Every semiconductor manufacturer measures the size of their devices in transmission electron microscopes," said Mecklenburg. "Now, in the same microscope, they can measure temperature gradients in an individual device."

Named Plasmon Energy Expansion Thermometry (PEET), this new technique can be used to effectively measure the temperatures within a transistor by measuring the expansion of materials already contained in the device.

"This technique is sensitive to the bulk material, not just the surface," said Mecklenburg. "Measurements of temperatures hidden inside a device will enable better thermal management, which means faster transistors and lower power consumption: your cell phone will hold its charge longer."

The research team also included USC Viterbi associate professor Stephen Cronin and electrical engineering doctoral student Rohan Dhall, William Hubbard and E.R. White of UCLA as well as Shaul Aloni of the Lawrence Berkeley National Laboratory.

The team will next translate this technique to other materials including silicon, a staple in transistors. Many common metals and semiconductors have the proper characteristics that will allow them to serve as their own thermometers. By applying PEET to other materials used in CPUs and transistors, researchers will be able to accurately map temperatures in microelectronic devices while they are in operation, as well as develop more efficient CPUs and transistors that dissipate less heat. 

This image shows simulation and observations of propagating plasmons in boron nitride heterostructure.

Graphene combined with the insulting power of boron nitride enables light control in tiny circuits with dramatically reduced energy loss

Squeezing light into tiny circuits and controlling its flow electrically is a holy grail that has become a realistic scenario thanks to the discovery of graphene. This tantalizing achievement is realized by exploiting so-called plasmons, in which electrons and light move together as one coherent wave. Plasmons guided by graphene -a two-dimensional sheet of carbon atoms - are remarkable as they can be confined to length scales of nanometers, up to two hundred times below the wavelength of light. An important hurdle until now has been the rapid loss of energy that these plasmons experience, limiting the range over which they could travel.

This problem has now been solved, as shown by researchers from ICFO (Barcelona), in a collaboration with CIC nanoGUNE (San Sebastian), and CNR/Scuola Normale Superiore (Pisa) ,all members of the EU Graphene Flagship, and Columbia University (New York).

Since the discovery of graphene, many other two-dimensional materials have been isolated in the laboratory. One example is boron nitride, a very good insulator. A combination of these two unique two-dimensional materials has provided the solution to the quest for controlling light in tiny circuits and suppression of losses. When graphene is encapsulated in boron nitride, electrons can move ballistically for long distances without scattering, even at room temperature. This research now shows that the graphene/boron nitride material system is also an excellent host for extremely strongly confined light and suppression of plasmon losses.

ICFO Prof Frank Koppens comments that "it is remarkable that we make light move more than 150 times slower than the speed of light, and at lengthscales more than 150 times smaller than the wavelength of light. In combination with the all-electrical capability to control nanoscale optical circuits, one can envision very exciting opportunities for applications."

The research, carried out by PhD students Achim Woessner (ICFO) and Yuando Gao (Columbia) and postdoctoral fellow Mark Lundeberg (ICFO), is just the beginning of a series of discoveries on nano-optoelectronic properties of new heterostructures based on combining different kinds of two-dimensional materials. The material heterostructure was first discovered by the researchers at Columbia University. Prof. James Hone comments: "Boron nitride has proven to be the ideal 'partner' for graphene, and this amazing combination of materials continues to surprise us with its outstanding performance in many areas".

Prof. Rainer Hillenbrand from CIC nanoGUNE comments: "Now we can squeeze light and at the same time make it propagate over significant distances through nanoscale materials. In the future, low-loss graphene plasmons could make signal processing and [super]computing much faster, and optical sensing more efficient."

The research team also performed theoretical studies. Marco Polini, from CNR/Scuola Normale Superiore (Pisa) and the IIT Graphene Labs (Genova), laid down a theory and performed calculations together with his collaborators. He explains that "according to theory, the interactions between light, electrons and the material system are now very well understood, even at a fully microscopic level. It is very rare to find a material that is so clean and in which this level of understanding is possible".

These findings pave the way for extremely miniaturized optical circuits and devices that could be useful for optical and/or biological sensing, information processing or data communications.

Researchers at The University of Texas at Austin's Cockrell School of Engineering have created the first transistors made of silicene, the world's thinnest silicon material. Their research holds the promise of building dramatically faster, smaller and more efficient computer chips.

Made of a one-atom-thick layer of silicon atoms, silicene has outstanding electrical properties but has until now proved difficult to produce and work with.

Deji Akinwande, an assistant professor in the Cockrell School's Department of Electrical and Computer Engineering, and his team, including lead researcher Li Tao, solved one of the major challenges surrounding silicene by demonstrating that it can be made into transistors --semiconductor devices used to amplify and switch electronic signals and electrical power.

The first-of-their-kind devices developed by Akinwande and his teamrely on the thinnest of any semiconductor material, a long-standing dream of the chip industry, and could pave the way for future generations of faster, energy-efficient  supercomputer chips. Their work was published this week in the journal Nature Nanotechnology.

Until a few years ago, human-made silicene was a purely theoretical material. Looking at carbon-based graphene, another atom-thick material with promise for chip development, researchers speculated that silicon atoms could be structured in a broadly similar way.

Akinwande, who also works on graphene transistors, sees value in silicene's relationship to silicon, which chipmakers already know how to work with.

"Apart from introducing a new player in the playground of 2-D materials, silicene, with its close chemical affinity to silicon, suggests an opportunity in the road map of the semiconductor industry," Akinwande said. "The major breakthrough here is the efficient low-temperature manufacturing and fabrication of silicene devices for the first time."

Despite its promise for commercial adaptation, silicene has proved extremely difficult to create and work with because of its complexity and instability when exposed to air.

To work around these issues, Akinwande teamed with Alessandro Molle at the Institute for Microelectronics and Microsystems in Agrate Brianza, Italy, to develop a new method for fabricating the silicene that reduces its exposure to air. To start, the researchers let a hot vapor of silicon atoms condense onto a crystalline block of silver in a vacuum chamber. They then formed a silicene sheet on a thin layer of silver and added a nanometer-thick layer of alumina on top. Because of these protective layers, the team could safely peel it of its base and transfer it silver-side-up to an oxidized-silicon substrate. They were then able to gently scrape some of the silver to leave behind two islands of metal as electrodes, with a strip of silicene between them.

In the near-term, Akinwande will continue to investigate new structures and methods for creating silicene, which may lead to low-energy, high-speed digital supercomputer chips.

The U.S. Army Research Laboratory's Army Research Office, the Cockrell School's Southwest Academy of Nanoelectronics and the European Commission's Future and Emerging Technologies Programme funded Akinwande's research.

Technique From Berkeley Lab’s Molecular Foundry Could Also Work with Graphene

“Cool it!” That’s a prime directive for microprocessor chips and a promising new solution to meeting this imperative is in the offing. Researchers with the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have developed a “process friendly” technique that would enable the cooling of microprocessor chips through carbon nanotubes.

Frank Ogletree, a physicist with Berkeley Lab’s Materials Sciences Division, led a study in which organic molecules were used to form strong covalent bonds between carbon nanotubes and metal surfaces. This improved by six-fold the flow of heat from the metal to the carbon nanotubes, paving the way for faster, more efficient cooling of computer chips. The technique is done through gas vapor or liquid chemistry at low temperatures, making it suitable for the manufacturing of computer chips.

“We’ve developed covalent bond pathways that work for oxide-forming metals, such as aluminum and silicon, and for more noble metals, such as gold and copper,” says Ogletree, who serves as a staff engineer for the Imaging Facility at the Molecular Foundry, a DOE nanoscience center hosted by Berkeley Lab. “In both cases the mechanical adhesion improved so that surface bonds were strong enough to pull a carbon nanotube array off of its growth substrate and significantly improve the transport of heat across the interface.”

Ogletree is the corresponding author of a paper describing this research in Nature Communications. The paper is titled “Enhanced Thermal Transport at Covalently Functionalized Carbon Nanotube Array Interfaces.” Co-authors are Sumanjeet Kaur, Nachiket Raravikar, Brett Helms and Ravi Prasher.

Overheating is the bane of microprocessors. As transistors heat up, their performance can deteriorate to the point where they no longer function as transistors. With microprocessor chips becoming more densely packed and processing speeds continuing to increase, the overheating problem looms ever larger. The first challenge is to conduct heat out of the chip and onto the circuit board where fans and other techniques can be used for cooling. Carbon nanotubes have demonstrated exceptionally high thermal conductivity but their use for cooling microprocessor chips and other devices has been hampered by high thermal interface resistances in nanostructured systems.

“The thermal conductivity of carbon nanotubes exceeds that of diamond or any other natural material but because carbon nanotubes are so chemically stable, their chemical interactions with most other materials are relatively weak, which makes for  high thermal interface resistance,” Ogletree says. “Intel came to the Molecular Foundry wanting to improve the performance of carbon nanotubes in devices. Working with Nachiket Raravikar and Ravi Prasher, who were both Intel engineers when the project was initiated, we were able to increase and strengthen the contact between carbon nanotubes and the surfaces of other materials. This reduces thermal resistance and substantially improves heat transport efficiency.”

Sumanjeet Kaur, lead author of the Nature Communications paper and an expert on carbon nanotubes, with assistance from co-author and Molecular Foundry chemist Brett Helms, used reactive molecules to bridge the carbon nanotube/metal interface – aminopropyl-trialkoxy-silane (APS) for oxide-forming metals, and cysteamine for noble metals. First vertically aligned carbon nanotube arrays were grown on silicon wafers, and thin films of aluminum or gold were evaporated on glass microscope cover slips. The metal films were then “functionalized” and allowed to bond with the carbon nanotube arrays. Enhanced heat flow was confirmed using a characterization technique developed by Ogletree that allows for interface-specific measurements of heat transport.

“You can think of interface resistance in steady-state heat flow as being an extra amount of distance the heat has to flow through the material,” Kaur says. “With carbon nanotubes, thermal interface resistance adds something like 40 microns of distance on each side of the actual carbon nanotube layer. With our technique, we’re able to decrease the interface resistance so that the extra distance is around seven microns at each interface.”

Although the approach used by Ogletree, Kaur and their colleagues substantially strengthened the contact between a metal and individual carbon nanotubes within an array, a majority of the nanotubes within the array may still fail to connect with the metal. The Berkeley team is now developing a way to improve the density of carbon nanotube/metal contacts. Their technique should also be applicable to single and multi-layer graphene devices, which face the same cooling issues.

“Part of our mission at the Molecular Foundry is to help develop solutions for technology problems posed to us by industrial users that also raise fundamental science questions,” Ogletree says. “In developing this technique to address a real-world technology problem, we also created tools that yield new information on fundamental chemistry.”

This work was supported by the DOE Office of Science and the Intel Corporation.

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