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SRC Computers, Inc., a leader in reconfigurable computing systems, demonstrated its implementation of a Black-Scholes double precision floating point algorithm, one of the most important mathematical tools in modern finance, on its newest Series I MAP reconfigurable processor at the Supercomputing 2007 show in Reno, Nev. The application level computational performance of the Series I MAP is over 150 million Black-Scholes experiments per second. This level of performance is equivalent to over 30 high-end microprocessors while consuming only 20 watts of power, making systems with the Series I MAP extremely cost-effective high performance computing solutions. Systems built with the Series I MAP will use SRC’s Carte high-level language programming environment and will be the first SRC product available using AMD Opteron processor-based boards. As a result, applications developed for SRC systems will be software compatible regardless of the microprocessor type. According to Jon Huppenthal, President and CEO of SRC, “The Series I MAP incorporates SRC’s reconfigurable MAP processor and high bandwidth SNAP interconnect into a single module that does not consume a microprocessor socket. This allows a four-processor AMD motherboard to be populated with four microprocessors and four MAPs, creating the highest density single board processing solution available. Such density can only be achieved with AMD’s processor interconnect and memory architecture.” "As customers demand more processing capabilities, acceleration technologies can offer significant performance gains," said Douglas O'Flaherty, AMD Division Manager for Acceleration Strategies. "Combining the Series I MAP with systems built using Quad-Core AMD Opteron processors can provide an incredibly dense computing solution. This is a great example of the customer-driven innovation that is possible when companies combine the AMD64 platform with their market experience and creative system design." Systems built with the Series I MAP are part of the SRC-7 product line, which includes SRC’s flagship systems using the feature-rich Series H MAP. The entire SRC-7 product line maximizes performance by using Altera FPGAs, which include the largest FPGAs available today. “The Series I MAP processor from SRC, together with their Carte Programming Environment, provide an industry-leading C and Fortran acceleration solution which excels in both ease-of-use and performance,” stated Mike Strickland, Director of Strategic and Technical Marketing in Altera Corporation’s Applications Business Group. “By utilizing Altera’s Stratix FPGAs in these high performance computing solutions, overall system performance is maximized and the highest power efficiency realized.” Production systems with the Series I MAP are expected to be available in the fourth quarter of 2007. The Black-Scholes demonstration can be viewed at the OpenFPGA booth #186.